D6 Output Enable Delay (output enable register to I/O buffer) logic option

A logic option that specifies the propagation delay from the I/O buffer to the output enable register for the D6 output enable delay cell. This is an advanced option; use this option only after compiling your project, checking I/O timing, and determining that timing is unsatisfactory. This option is ignored if it is applied to anything other than an input or bidirectional pin.

Scripting Information

Keyword: d6_oe_delay

Settings: <integer>


For more information, refer to the data sheet for the relevant device family, which is available from the Literature section of the Altera website.