PLL Automatic Self Reset logic option

This logic option automatically self-resets the PLL upon loss of lock. The lock time of a PLL is defined as the amount of time required by the PLL to attain the target frequency and phase relationship after device power-up, after a change in the PLL output frequency, or after resetting the PLL.

A PLL might lose lock for any of the following reasons:

  • Excessive jitter on the reference clock.
Note: For PLL input jitter specification, refer to the DC and Switching Characteristic information in the relevant FPGA device documentation.
  • Excessive switching noise on the clock inputs of the PLL.
  • Excessive noise from the power supply can cause high output jitter and possible loss of lock.
  • A glitch or stopping of the input clock to the PLL.
  • Resetting the PLL by asserting the reset port of the PLL.
  • An attempt to reconfigure the PLL might cause the M counter, N counter, or phase shift to change, which causes the PLL to lose lock. However, changes to the post-scale counters do not affect the PLL locked signal.
  • PLL reference clock frequency drifts outside the lock range specification.

This option is available for the Stratix® V device family only.

Scripting Information

Keyword: pll_auto_reset

Settings: on | off