Ignore translate_off and synthesis_off Directives logic option

A logic option that instructs Analysis & Synthesis to ignore all of the translate_off and synthesis_off Verilog HDL and VHDL synthesis directives in your current design. For example, if your design includes the following synthesis directives:

// synthesis translate_off


// synthesis synthesis_off

You can use this option to disable these synthesis directives and include previously ignored sections during compilation.

You can use this option to compile code that was previously ignored by third-party synthesis tools, for example, Intel® FPGA IP declarations that were treated as black boxes in other tools, but can be compiled in the Intel® Quartus® Prime software.

Scripting Information

Keyword: ignore_translate_off_and_synthesis_off

Settings: on | off*