ID:22849 SDM PLL is missing. Cannot generate a 250MHz clock.Make sure DEVICE_INITIALIZATION_CLOCK is set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ in the QSF file.

CAUSE: The correct settings to enable SDM PLL were not set.

ACTION: Set DEVICE_INITIALIZATION_CLOCK to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ in the QSF file.