To perform gate-level functional simulation with the ModelSim® GUI

  1. If you plan to use device-wide reset or power-on signals available in the Verilog Output File (.vo) Definition, VHDL Output File (.vho) Definition, or SystemVerilog Output File (.svo), if you have not already done so, ensure that these signals are driven appropriately during simulation.
  2. On the Simulate menu, click Simulate.
  3. If you are simulating a Verilog HDL design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.
  4. Click the Design tab.
  5. In the Name list, expand the work directory and select the design entity that corresponds to the .sdo.
  6. Click Add.
  7. Select the top-level .vo, .svo, .vho, or testbench.
  8. Click Add.
  9. If you are simulating high-speed circuits (including designs that use HSSI, LVDS, or PLLs):
    1. Click the Other tab.
    2. In the Other options box type +transport_int_delays and +transport_path_delays.
    3. Click OK.
  10. Click Load.
  11. To direct the ModelSim® software to generate a Value Change Dump File (.vcd) Definitionthat you can then use to perform power analysis in the Intel® Quartus® Prime Power Analyzer, type the following command at the ModelSim® prompt:
    source<testbench or design instance name>_dump_all_vcd_nodes.tcl

    The Tcl Script File (.tcl) directs the ModelSim® software to monitor and write the output signals contained in the Tcl Script File to a .vcd during simulation.

  12. Perform the gate-level functional simulation in the ModelSim® software.