Iteration limit for constant Verilog loops logic option

A logic option that defines the iteration limit for Verilog loops with loop conditions that evaluate to compile time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or place the Intel® Quartus® Prime software in an infinite loop.

This option must be assigned to an entity or it is ignored.

Scripting Information

Keyword: verilog_constant_loop_limit

Settings: <integer>

default = 5000