Delay from Output Register to Output Pin logic option

A logic option that specifies the propagation delay to the output or bidirectional pin from the output register implemented in an I/O cell. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.

This option is useful for fine-tuning the I/O timing of your design and meeting tCO requirements.

This option defaults to 0. Legal integer values are 0 or 1. Actual delay values are 58ps for a setting of 0 and 558ps for a setting of1. This option must be assigned to an output or bidirectional pin or it is ignored.

Scripting Information

Keyword: clock_to_output_delay

Settings: 0 | 1