Set Minimum Delay Dialog Box (set_min_delay)

You access this dialog box by clicking Constraints > Set Minimum Delay in the Timing Analyzer, or with the set_min_delay Synopsys^® Design Constraints (SDC) command.

Allows you to override the default hold constraint for any path with a specific minimum time value for the path. You can specify the source (-from), common through elements (- thru), and destination (-to) elements of the path included in the minimum delay value.

Minimum delays are always relative to any clock network delays (if the source or destination is a register) or any input or output delays (if the source or destination is a port). Thus, input delays and clock latencies are added to the data arrival times; clock latencies are added to data required times; and output delays are subtracted from data required times.

The following sections provide more information about specifying options for this constraint:

From (-from):

Specifies the source ( collection Definition of clocks, registers, ports, pins, or cells) in the path to which you want to apply the minimum delay. You can use the Name Finder (...) to build a collection.

Through (-through):

Specifies the common through elements ( collection Definition of pins or nets in the design) in a path to which the timing constraint or exception applies. You can use the Name Finder (...) to build a collection.

Scripting Information

Keyword: keyword_info

Settings: on | off*

*default

Note: You cannot set this option if you specify clocks for the source (-from) or destination (-to) elements.

To (-to):

Specifies the destination ( collection Definition of clocks, registers, ports, pins, or cells) in a path to which the timing constraint or exception applies. You can use the Name Finder (...) to build a collection.

Delay value:

Specifies the minimum required delay for the path.

SDC command:

Displays and allows you to enter SDC commands for the options you specify in this dialog box.

If you specify a clock as the collection for the source (-from) element, you must specify a clock for the collection in the destination (-to) element. Applying exceptions between clocks applies the exception from all registers or ports clocked by the source (-from) clock to all registers or ports clocked by the destination (-to) clock. Applying exceptions between clocks is more efficient than applying them for specific paths.

If you specify pin names or collections of pins, the source (-from) element must be a clock pin, and the destination (-to) value must be any non-clock input pin to a register. Constraints from clock pins, or to and from cells, apply to all registers in the cell or those clocked by the clock pin.