Derive PLL Clocks (derive_pll_clocks)

You access the functions of this dialog box by clicking Timing Analyzer's Constraints > Derive PLL Clocks, or with the derive_pll_clocks Synopsys® Design Constraints (SDC) command.

Causes the Timing Analyzer to find all unconstrained PLL output clocks in the timing netlist.

Note: You should update your timing netlist after running the Derive Clock Uncertainty command.

Create base clocks:

Turn on Create base clocks to create base clocks on the inputs of the PLLs. This option is on by default.

Use net name as clock name:

Directs the Derive PLL Clocks command to create the constraint using the net name for the clock name.

SDC Command:

Displays SDC commands for the options you specify in this dialog box.