Create Clock Dialog Box (create_clock)

Allows you to define the properties and constraints of a new clock in the design. You specify the clock name (-name), clock period (-period), rising and falling waveform edge values (-waveform), and the target signal(s) to which the constraints apply.

The following sections provide more information about specifying options for this constraint:

Clock name (-name):

Allows you to specify a unique name for the clock. If you do not specify a name for the clock, the Timing Analyzer uses the first name specified in the Targets box. You use the clock name to refer to the clock when specifying other timing constraints.

Period (-period):

Allows you to define the clock period using default time units.

Waveform edges (-waveform):

Allows you to define the rising and falling edges of the clock waveform. The rising edge must be within the range [0, clock period). The falling edge must be within one clock period from the rising edge. The waveform default value is {0 clock period/2}.

Targets:

Allows you to specify the targets to which the constraint applies. If the target is an internal element (that is, not an input port), the default source latency is zero. If the specified target already has a clock definition, the Timing Analyzer overwrites the original clock definition for that target unless you use the command-line interface to specify the -add option. You can use the -add option to assign multiple clocks to a pin or port. If the constrained clock is on a path following another clock, then the Create Clock constraint blocks or overwrites the previous clock from that point and after. If you do not specify a target, the Timing Analyzer creates a virtual clock. You can use the Name Finder (...) to build a collection Definition of targets.

SDC command:

Displays and allows you to enter SDC commands for the options you specify in this dialog box.