PLL External Feedback Board Delay logic option

A logic option that specifies an external board delay between a feedback output pin and a feedback input pin (fbin) for a PLL in external feedback mode.

This option is useful for describing the external board delay between a feedback output pin and a feedback input pin for the PLL in external feedback mode. Because the board delay is part of the PLL feedback path, the Intel^® Quartus^® Prime software can use the board delay to correctly calculate the PLL compensation delay.

This option must be assigned to the fbin pin of a PLL or it is ignored.

This option is available for supported device (Arria^® series, Stratix^® III, and Stratix^® IV) families.