Perform Asynchronous Signal Pipelining logic option

A logic option that directs the Intel^® Quartus^® Prime software to perform automatic insertion of pipeline stages for asynchronous clear and asynchronous load signals during fitting to increase circuit performance. This option is useful for asynchronous signals that are failing recovery and removal timing because they feed registers using a high-speed clock.

The following examples illustrate typical situations where automatic asynchronous signal pipelining is used.

To run the automatic asynchronous signal pipelining algorithm, the signal must meet the following requirements:

1. The signal is estimated to be critical.
   Note:

   • Because estimation is performed before placement, in some cases, the estimation may be incorrect at design completion. Use the Automatic Asynchronous Signal Pipelining Register Reach and Netlist Optimizations assignments to specify whether or not to force the algorithm to pipeline a specific signal in the design.
2. The signal is generated by a synchronization register or buffer.
3. The signal must fan-out exclusively to the asynchronous register inputs and I/O pins.
4. The signal does not cross partition boundaries.

This option is available for supported device (Arria^® series, Cyclone^® series, MAX^® II, MAX^® V, and Stratix^® series) families.