EDA Tool Settings Page (Settings Dialog Box)
You open this page by clicking EDA Tool
Settings in the Settings: dialog
box.
You can optionally integrate supported EDA synthesis, netlist partitioning, simulation, and signal integrity verification tools into the Intel® Quartus® Prime design flow.
The EDA Tool Settings page allows you to specify supported third-party tools and options to perform the design entry/synthesis, simulation, or board-level signal integrity analysis portions of the overall design flow. After specifying a supported third-party tool, the Intel® Quartus® Prime can automatically generate integration files to interface with your third-party tool each time you run a full compilation or run the EDA Netlist Writer.
The following options are available:
Option | Description |
---|---|
Run EDA Netlist Writer during compilation | Automatically runs the EDA Netlist Writer to generate third-party tool intergration files each time you run full compilation. |
Design entry/synthesis | |
Tool name | The available options are:
|
Simulation | |
Tool name | The available options are:
|
Format for output netlist | The available options are:
|
Output directory | Specifies the directory that saves the generated third-party tool integration files after running EDA Netlist Writer. By default, board/<format>/. |
Map illegal HDL characters | Directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL. By default, simulation/<vendor name>/ |
Board-level signal integrity analysis | |
Format | The only available option is IBIS. |
IBIS version | You can specify either 4.2 or 5.0. |
Output directory | Specifies the directory that saves the generated third-party tool integration files after running EDA Netlist Writer. By default, board/<format>/ |
Enable model selector | Enables the model selector option. |
Enable extended model selector | Enables the extended model selector option. |
Print per pin RLC package model with mutual coupling | Prints a per pin RLC package model with mutual coupling. |