reset_design (::quartus::sdc)

The following table displays information for the reset_design Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc 1.5

Syntax reset_design [-h | -help] [-long_help]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
Removes all assignments from the design. This includes clocks,
generated clocks, derived clocks, input delays, output delays, clock
latency, clock uncertainty, clock groups, false paths, multicycle
paths, min delays, and max delays. After reset_design is called, the
design should be in the same state as it would be if
create_timing_netlist was just called.
Example Usage
# Constrain design
create_clock -name clk -period 4.000 -waveform { 0.000 2.000 } [get_ports clk]
set_input_delay -clock clk2 1.5 [get_ports in*]
set_output_delay -clock clk 1.6 [get_ports out*]
set_false_path -from [get_keepers in] -through [get_nets r1] -to [get_keepers out]

# Reset the design to the state that it was in before any constraints were entered
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.