SEU FIT Report

Intel’s reliability reports show raw SEU data. This data is the FIT rate that the design would have if every configuration RAM bit, M20K bit, and every flipflop in the chip were used. Although this report provides unambiguous data, it is highly pessimistic. For example, even a 100% full design does not use 100% of its available routing, some LUTs are not full 6-input LUTs, and most designs do not use all available hard IP blocks.

The FIT calculator provides a design-specific SEU report for the specified device. The calculator iterates through the design components and computes all bits (the raw FIT), utilized bits (only resources the design actually uses), and the ECC-mitigated bits.

Note: The Intel^® Quartus^® Prime software counts device bits for target devices using different parameter information than the Reliability Report. Therefore, expect a ±5% variation in the Projected SEU FIT by Component Usage report Raw column compared to the Reliability Report data. For additional information about SEU, refer to the SEU Mitigation User Guide for your specific FPGA device.

Raw

Raw FIT is the FIT rate of the device if every cell is used. The FIT report shows the raw FIT in the first column of the report with the breakdown across logical categories and cell types.

Utilized

The report’s utilized FIT restricts the calculation to the bits that the design actually uses. For example, if the design does not use a LUT or routing multiplexer, the report does not count those bits for the utilized FIT. Intel devices can tolerate SEU events in unused resources without affecting the device. Therefore, you can safely ignore these bits for resiliency statistics.

w/ECC

You can lower the FIT by taking action to reduce the observed FIT rate, for example, by mitigating memory ECC FIT. You can also mitigate FIT using the optional ECC on M20K blocks as well as the (not optional) ECC on the hard processor and other hard-IP such as memory controllers, PCIe, and I/O calibration blocks. For consistency, the report shows the full FIT classification as a column. However, ECC does not affect CRAM and flipflop rates; therefore, the data for these cell types in this column is the same as the Utilized column.

Architecture Vulnerability Factor (AVF)

The last two columns, AVF 0.5 and AVF 0.25, in the report show an architectural vulnerability factor (AVF). This factor is design dependent; .25 and .5 represent “reasonable” and “conservative” AVF, respectively.