Simulation Model Support

Only ModelSim^® or QuestaSim version 6.6c and later can read Intel^® Quartus^® Prime software version 10.1 and later IEEE encrypted simulation model files.

You can simulate Mentor Graphics^® Verilog HDL models in any single language Verilog HDL, VHDL, or mixed language version of ModelSim^® or QuestaSim.

When you simulate a VHDL design containing encrypted Verilog HDL models, Mentor Graphics^® single and mixed language simulators consume one simulator license.

Similarly, version 10.1 and later simulation model files that are IEEE encrypted for Aldec, Cadence, or Synopsys^® simulators, can be read only by the corresponding simulator. These encrypted simulation models are located in the /quartus/eda/sim_lib/<simulator> directory.

Some Intel FPGA IP cores provide additional encrypted models in the <simulator> subdirectories where your IP variant's simulation models are generated.

Note: For more information about compiling simulation models, refer to Preparing for Simulation.