RDC-50002: Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain
Description
Violations of this rule identify multiple reset synchronizer chains whose reset domains reach the same register. The violating chains synchronize the same reset signal. Since asynchronous reset synchronizers may not come out of reset on the same clock cycle, the logic reaching the nodes that belong in multiple reset domains may contain both active and reset data at the same time.
Recommendation
Use the output of the same reset synchronizer chain for resetting all registers in a fan-out cone. If the reset signal is timing critical, add a pipelined reset tree after the reset synchronizer to close timing.
If the reset domain crossing is intended, then you can ignore or waive the rule.
Severity
High
Tags
| Tag | Description |
|---|---|
| reset-usage | Design rule checks related to safe resets or appropriate use of reset modes. |
| reset-reachability | Design rule checks related to reachability analysis of reset signals, including convergence of mutiple reset signals. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel®Agilex™