LNT-30013: Design Contains Ripple Clock Structures


Ripple clock structures have the outputs of two or more registers in a cascade, with each directly driving the input clock port of the following register in the cascade.

Figure 1. Ripple Clock Structure

Each stage of a ripple clock structure causes phase delay, which accumulates and results in large skews in the structure's output signal. The large skew can cause timing closure problems when you use the ripple clock structure as a clock signal for other circuits. Each stage of a ripple clock structure also causes definition of a new clock domain. The additional clock domains make timing analysis of the design more complex and time-consuming.


Remove ripple clock structures in your design. Designers sometimes use ripple clock structures to make counters out of the smallest amount of logic possible. However, in the Intel Quartus Prime Pro Edition software, using a ripple clock structure to reduce the amount of logic used for a counter is unnecessary because you can construct a counter using one logic element per counter bit.




Tag Description
clock-skew Design rule checks related to clock skew.

Device Family

  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX