Alias logic option

Allows you to specify an alias for the full hierarchical name of a node during simulation.

This option is useful if you want to specify a different name, or alias, for a node that can be observed during simulation. For example, in a 1-wire design that contains an INPUT_A feeding an OUTPUT_B, you can specify the Alias option to rename the output signal waveform vector for the OUTPUT_B node to C ONTROL while maintaining the OUTPUT_B node name. This allows you to observe the behavior of the CONTROL_OUT node during a simulation.

This option must be assigned to a node or it is ignored.

Scripting Information

Keyword: alias

Settings: <alias name>