Input Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
probe[] |
Yes |
Specifies the probe port. |
Input port [probe_width - 1..0] wide. |
source_clk |
Yes |
Specifies the clock source. |
|
source_ena |
Yes |
Specifies the clock enable source. |
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
probe[] |
Yes |
Specifies the probe port. |
Input port [probe_width - 1..0] wide. |
source_clk |
Yes |
Specifies the clock source. |
|
source_ena |
Yes |
Specifies the clock enable source. |