Performing a Gate-Level Functional Simulation with the ModelSim® Software

You can perform a gate-level functional simulation of a Verilog HDL or VHDL design with the Mentor Graphics® ModelSim® PE or SE software with the ModelSim® GUI or at command-line.

Note: For more information about using EDA simulators, refer to the Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation.