LNT-30012: Design Contains Latches


Latches are structures where two sets of two-input combinational logic (which the Compiler implements in logic cells) are cross-coupled using combinational loops. These combinational loops drive the output of one set of logic to an input of the other set of logic.

Note: Often, latches are implemented unintentionally due to RTL coding error. This rule helps detect those RTL errors.

A latch can cause glitches and ambiguous timing in a design, which makes timing analysis of the design difficult. In addition, a latch can cause significant stability and reliability problems in a design. This stability problem is because the behavior of the combinational loops in the latch often depend on the relative propagation delays of the combinational loop's logic, causing the combinational loop to behave differently under different operation conditions.

Figure 1. SR-Latch
Figure 2. D-Latch Based on an SR Latch


Remove the latches from your design.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.
latch Design rule checks related to latches.

Device Family

  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX