register pipelining Definition

A feature that allows you to register a Signal Probe signal with a user-specified clock and a user-specified number of registers. Register pipelining can be used to ignore jitter, to force signal states to output on a clock edge, or to delay a signal output. You can also use register pipelining to synchronize multiple Signal Probe outputs from a bus of signals, or to prevent Signal Probe routing from becoming the critical path because of fMAX changes.

This feature is available only for MAX^® II.