ID:228002 Physical synthesis settings are on -- do you still want to back-annotate? Back-annotation will be unreliable unless you output a Verilog Quartus Mapping File and use it as the design source with your back-annotation.
CAUSE: You specified one or more options for optimizing netlists during fitting, and attempted to back-annotate the current design. However, the Quartus Prime software cannot perform these netlist optimizations on a back-annotated design. If you simply back-annotate, and re-run the Quartus Prime software with same design source files, your back-annotated location, routing and/or LogicLock assignments will not match the design netlist in the subsequent fit. This will usually lead to poor performance or no-fits, since the assignments will be mismatched and constrain the Fitter in unpredictable ways.
ACTION: Click Yes to back-annotate the design, or click No to cancel the operation. For reliable back-annotation with fitter netlist optimizations on, you must do the following:
- Save a node-level Verilog Quartus Mapping File (.vqm).
- Make the VQM File the single design source file in your project. You may want to duplicate your project and make this edit in a new project so you still have the original project with the original source files in case you need to make design changes.
- Disable all the Fitter netlist optimizations.