ID:13479 Verilog Module Declaration warning at <location>: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "<name>"

CAUSE: In a Verilog Design File (.v) at the specified location, you declared the specified module. However, the Module Declaration's port list for the module contains duplicate or dangling commas, which represent anonymous ports with no names. Because the extra commas are probably typographical errors, the Quartus Prime software ignored the duplicate or dangling commas. For example, in the following code, the module port list contains a duplicate comma (,,) and a dangling comma (,)):

module foo(clk, reset, d,, q,)

               
   input clk, reset, d;
   output q;

               
    ...

               
endmodule