ID:13512 Verilog HDL Case Statement warning at <location>: size of case item expression (<number>) exceeds the size of the case expression (<number>)
CAUSE: In a Case Statement in a Verilog Design File (.v), you used a case item expression whose size is larger than the size of the case expression. As a result, the case item expression may never match the case expression. For example, in the following Verilog HDL code, the final case item contains a 3-bit constant literal expression. However, the case expression is only two bits wide. Though the case expression is zero-extended before comparison to the case items, it will never match the final case item, and the Case Statement is therefore incomplete.
reg [1:0] sel; reg [3:0] o; always@(sel) begin case(sel) 2'b00: o = 4'b1010; 2'b01: o = 4'b0101; 2'b10: o = 4'b1111; 3'b111: o = 4'b0000; // 3-bit case item expr larger than 2-bit case expr endcase end
ACTION: To prevent this message, revise the case item expression so that its size is smaller than or equal to the size of the case expression.