ID:13568 SystemVerilog warning at <location>: unique case statement has overlapping case items

CAUSE: In a case statement at the specified location in a SystemVerilog Design File (.sv), you indicated that the case item expressions were unique with the unique keyword. However, at least one case item expression overlaps with an expression in another case item. Quartus Prime Integrated Synthesis will not implement priority logic for this case statement but will honor your expressed intent. The simulated behavior of your design may not match the behavior of the synthesized netlist. A SystemVerilog-compliant simulator should issue a warning if, during simulation, multiple case item expressions match the case expression.

ACTION: No action is required. To eliminate the warning, remove the overlap.