ID:13033 The <name> "<name>" is fed by <name>

CAUSE: The specified node or pin is fed by VCC or GND, but the Quartus Prime software expects it to be fed by tri-stated logic. For example, the following Verilog design gives this warning for the bidirectional pins bidir1 and bidir2.

		module test1 (inout bidir1, bidir2); 
		assign vcc = 1'b1; 
		assign gnd = 1'b0; 
		assign bidir1 = vcc; 
		assign bidir2 = gnd; 
		endmodule