ID:176255 Can't pack node <name> and I/O node <name> -- synchronous clear signal violation

CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the nodes because the I/O cell already contains a register that has a different synchronous clear signal than the register to be packed. Each I/O can have only one distinct synchronous clear signal. The I/O cell does not have an sload port, so any existing sload ports on the logic cell must be converted to an sclear on the I/O pin. If the two nodes have one sclear signal, there might be other registers in the design which also had one of the above logic options turned on. If these registers were packed with the I/O cell in an earlier phase of register packing, there might be conflicting sclear signals because Analysis & Synthesis generally does not pack registers into I/O cells.

ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, make sure that the specified nodes have the same synchronous clear signal.