ID:176070 Can't merge fast PLL <name> and fast PLL <name> -- merged fast PLL would drive <number> DPA channels, but a fast PLL can drive a maximum of <number> DPA channels when placed in center (based on the maximum distance allowed between DPA channels per bank and using both the top and bottom banks)

CAUSE: The Fitter cannot merge the specified fast PLLs because the merged fast PLL would drive the specified number of dynamic phase alignment (DPA) channels, which is greater than the maximum specified. This message is a submessage of the message that precedes it in the Messages window and in the Messages section of the Report window.

ACTION: Modify the design to reduce the number of DPA channels driven by the specified fast PLLs to below the maximum number specified.