ID:308071 (Medium) <text>. (Value defined:<number>). Found <number> asynchronous clock domain interface structure(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of structures where data is transferred between asynchronous clock domains, but all of the data bits are synchronized. If the data bits belong to multiple-bit data, only the data bits that act as REQ (Request) and/or ACK (Acknowledge) signals for the transfer should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. If the data bits belong to single-bit data, the synchronization of all the data bits does not cause problems in the design. The submessage(s) of this message list the structure(s) that the Design Assistant found.

ACTION: Determine if the data bits belong to multiple-bit or single-bit data. If the data bits belong to multiple-bit data, synchronize only the data bits that act as REQ and/or ACK signals, and remove the synchronization of the other signals. If the data bits belong to single-bit data, no action is required.