ID:308027 (Medium) <text>. Found <number> node(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of nodes where a reset signal is generated in one clock domain and used in one or more other, asynchronous clock domains. However, the reset signal is not synchronized, which can cause metastability problems in the design. In addition, a reset signal that is not correctly synchronized can cause the output of registers in the receiving asynchronous clock domain to send incorrect signals, which can cause primary output pins in the device to momentarily send incorrect signals. Therefore, the reset signal should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the node(s) that the Design Assistant found.

ACTION: Synchronize the reset signal.