ID:308022 (Medium) <text>. Found <number> node(s) related to this rule.

CAUSE: The Design Assistant found the specified number of nodes where you connect a clock signal source (for example, an input clock pin) so that it drives the design's registers in one of the following ways:

The clock signal source drives registers that have clock inputs that trigger on the positive edge of the clock, and other registers that have clock inputs that trigger on the negative edge of the clock.
The clock signal source drives only registers that have clock inputs that all trigger on either the positive or negative edge of the clock, but the design inverts the clock before driving some of the registers.

These connections can cause various design problems, including an increase in timing requirement complexity and difficulties when optimizing a design for the HardCopy device. Additionally, because registers are not clocked on the same edge in the design, synchronous resetting is impossible. When a design inverts the clock, additional design problems might occur; for example, the inverted clock might be mapped to regular logic or might not contain the correct time relationship to the original clock.

The registers that synchronize combinational logic used as a clock or reset signal are sometimes triggered by different clock edges. However, these registers do not cause problems in the design.

The submessage(s) of this message list the node(s) that the Design Assistant found.

ACTION: No action is required. To avoid receiving this message in the future, make sure that only the positive clock edge or negative clock edge triggers the clock inputs in all the registers of the design, and that the design does not invert the clock before the clock signal source drives one or more registers.