ID:15055 PLL "<name>" input clock inclk[<number>] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.

ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.