ID:11195 ATX PLL node "<name>" uses a frequency that may not be supported on all ATX PLLs.

CAUSE: ATX phase-locked loop (PLL) on production silicon has frequency limitations based on placement.

ACTION: Refer to Stratix V Errata Sheet to ensure that the data rate for the specified ATX PLL is within the documented performance specification for the placement. Otherwise, manually assign this ATX PLL to the appropriate location based on the Stratix V Errata Sheet."