ID:276012 RAM logic "<name>" is uninferred due to too many ports

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as true dual port RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because more than two unique addresses are used.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that the RAM uses at most two unique addresses.