ID:13406 Verilog HDL error at <location>: object "<name>" is not declared

CAUSE: In a Verilog Design File (.v) at the specified location, you referred to an object with the specified name. However, Quartus Integrated Synthesis was unable to match the name to an object whose declaration is visible in the current scope.

ACTION: Check the name for possible misspellings. Otherwise, declare the object.