ID:13488 Verilog HDL Module Instantiation error at <location>: Module Instance Parameter Value Assignment list contains more than one assignment for parameter "<name>"

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you used a Module Instance Parameter Value Assignment list to assign values to the parameters of a module instance. However, the list contains more than one value assignment for the specified parameter. You may specify a value to a specific parameter at most once in a Module Instance Parameter Value Assignment list.

ACTION: Specify a value for a parameter at most once in a Module Instance Parameter Value Assignment list.