ID:13571 SystemVerilog error at <location>: can't declare packed array dimension with a single-valued range

CAUSE: In a Verilog Design File (.v) or SystemVerilog Design File (.sv), you declared a packed array dimension with a single-valued range. SystemVerilog allows you to declare unpacked array dimensions with a single-valued range but requires you to specify explicit left and right bounds for packed array dimensions.

ACTION: Specify explicit left and right bounds for the packed array dimension.