ID:13569 SystemVerilog error at <location>: can't connect expression with incompatible data type to formal "<name>"

CAUSE: In a SystemVerilog Design File (.sv) at the specified location, you connected an expression (the actual) to the specified port or argument (the formal). However, the expression has an invalid type. For formal inputs, the actual data type must be assignment compatible to the formal data type. For formal outputs, the formal data type must be assignment compatible to the actual data type. For formal inouts, the formal and actual data types must be mutually assignment compatible.

ACTION: Modify the data type of the formal, the actual, or both to make them assignment compatible. If possible, use a type cast to force assignment compatibility without modifying the data types, or remove the connection altogether.