ID:275067 Design name "<name>" is illegal for Verilog HDL

CAUSE: You created a Verilog Design File (.v) from the current design file. However, the current design name contains an illegal character for Verilog HDL, "/" or "-", or contains a Verilog HDL keyword. This can cause the Verilog Design File to not compile once it is generated.

ACTION: Rename the design to exclude illegal name characters or Verilog HDL keywords and create the HDL design file again.