ID:176571 Can't place <name> PLL "<name>" in PLL location <name> because its input clock "<name>" uses I/O standard <name> and has a frequency of <name> but PLL I/O pin <name> can only support a frequency up to <name>

CAUSE: You specified the input clock frequency and the specified I/O standard for the specified input pin, which is an input clock of the specified fast or enhanced PLL. However, the Fitter cannot place the fast or enhanced PLL because the input clock frequency is higher than the specified maximum input clock frequency that the target PLL I/O pin can support for the I/O standard.

ACTION: Modify the design so that the input clock frequency of the PLL is less than the maximum frequency or assign the specified input clock pin to a different location.