ID:170070 Cannot place logic cells assigned to one LAB into a single LAB
CAUSE: You created assignments such as location assignments, clique assignments, or Logic Lock region assignments. These assignments, along with carry or cascade chains between logic cells, forced a group of logic cells into one LAB. However, the group of logic cells cannot be placed in a single LAB. This message can occur when there are too many logic cells to fit in one LAB, or the logic cells require more signals (such as clock enables) than a single LAB can provide.
ACTION: Remove some of the location, LAB clique, and/or Logic Lock assignments to the cells constrained to lie in one LAB.
CAUSE: You back-annotated the contents of one or more Logic Lock regions after compiling the design with the Auto Packed Registers logic option turned on. During the initial compilation (that is, the compilation that produced the results that you back-annotated), the Fitter's register packing operation packed more logic cells into a single LAB than could otherwise fit into that LAB. As a result, you back-annotated more logic cells to a single LAB than can normally be assigned to a single LAB. However, during the current compilation, the Fitter did not recognize that this group of logic cells could be packed together to fit into a single LAB.
- Turn off the Auto Packed Registers logic option. or
- Compile an entity while saving intermediate synthesis results to generate a Verilog Quartus Mapping File (.vqm) for the current project. After compiling and back-annotating the design, but before recompiling, add the VQM File generated during the compilation to the current project and remove your original design files from the current project. Because the generated VQM File locks in the register packing performed during the initial compilation, the Fitter is able to recognize that the back-annotated cells assigned to a single LAB can be packed together to fit into a single LAB on subsequent compilations.
CAUSE: You imported Logic Lock region assignments from another project into the current project, but the imported assignments require more device resources than are available in the current project. For example, the logic cells that the imported assignments force into a single LAB may require more signals (such as clock enables) than a single LAB can provide. This message can occur if, in the project from which the assignments were imported, the Fitter promoted one of the required signals to a global signal in order to fit these logic cells into a single LAB, but, in the current project, there are not enough global signals available to perform this promotion. For example, if the entity for which you imported the assignments is instantiated multiple times in the current project, there may not be enough global signals to instantiate those assignments for each instance of the entity in the current project.
ACTION: Delete back-annotated assignments in the Logic Lock region containing the nodes listed in the submessages.