ID:12831 All pipeline register must share the same clock source for DSP block WYSIWYG primitive "<atom name>" and the input pipeline register must be enabled.

CAUSE: The specified DSP block WYSIWYG primitive have different pipeline register clock sources or the input pipeline register is not clocked. The input pipeline register must be enabled and all pipeline registers must share the same clock source.

ACTION: Make sure the input_pipeline_clock parameter is not set to none and change the pipeline register clock sources for the specified atom to be the same.