Assigning Design Constraints with the Precision RTL Synthesis Software

You assign design constraints in the Precision RTL synthesis software by creating a Synopsys Design Constraints File (.sdc) Definition containing the design constraints and adding it to the project.

Alternatively, you can set design constraints directly in the Precision RTL Synthesis software, and the Precision RTL Synthesis software creates a Synopsys Design Constraints File (.sdc) Definition named <design name>_constraints.sdc in the current project directory.

To set design constraints in the Precision RTL Synthesis software user interface:

  1. In the Design Hierarchy window, click the + icon to expand the Clocks folder.
  2. Right-click the clock, and click Set Clock Constraints.
  3. Set additional attributes for a clock, by right-clicking the clock, and clicking Set Attributes.
  4. To set timing and mapping constraints on ports:
    1. In the Design Hierarchy window, expand the Ports folder.
    2. Expand the Inputs or Outputs folder.
    3. Right-click a specific port and click Set Input Constraints or Set Output Constraints. The Port Constraints dialog box appears.
    4. Use the Port Constraints dialog box to set timing and mapping constraints, including pin numbers, I/O standards, and I/O pads.
    5. You can also right-click a specific port and click Force Register into I/O to force registers to be moved into I/O elements during synthesis.
  5. To disable I/O pad insertion on I/O pins in the design during synthesis:
    1. Click Set Options. The Synthesis Options dialog box appears.
    2. Select Optimization.
    3. Turn off Add IO Pads.
    4. Click OK.