CDC-50102: Synchronizer after CDC Bus with Control Signal
Description
Violations of this rule identify a synchronizer that was identified from the destination of a CDC bus managed by a control signal, such as a clock enable or MUX select signal. Such buses may not require being followed by a synchronizer, as they are already synchronized by the control signal.
Recommendation
To prevent synchronizers from being formed after such a bus, apply an instance assignment of Synchronization Register Chain Length = 1 on the head of the bus.
Severity
Low
Tags
| Tag | Description |
|---|---|
| synchronizer | |
| false-positive-synchronizer |
Device Family
- Intel® Cyclone® 10 GX
- Intel® Arria® 10
- Intel® Stratix® 10
- Intel® Agilex™