CDC-50004: MUX-type CDC Bus Transfer with Insufficient Constraints

Description

Violations of this rule identify a CDC bus transfer controlled by a MUX or a MUX-like topology with insufficient timing constraints. Without proper constraints, all bits of such a bus may not latch on the same clock cycle.

Figure 1. Topologies checked by CDC-50004.. MUX-type buses include topologies where one input of the MUX is tied to VCC or ground, as well as bus transfers controlled by synchronous clear, as the following figure shows.

Recommendation

Apply an instance assignment of Synchronization Register Chain Length = 1 on the head of a MUX-type CDC bus to prevent downstream registers from being treated as a synchronizer chain. Next, apply a set_max_skew constraint on the bits of the bus to ensure that all bits latch on the same clock cycle. The value of the skew constraint must be equal to or lower than either the source or destination clock period, whichever is lower. This can be accomplished with the following constraint:

set_max_skew -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier $value_between_0_and_1 -from [get_registers $source_registers] -to [get_registers $destination_registers]

Also, apply a set_data_delay constraint on the bits of the bus to limit their allowable delay. The value of the data delay constraint must be equal to or lower than the destination clock period. This can be accomplished with the following constraint:

set_data_delay -get_value_from_clock_period dst_clock_period -value_multiplier $value_between_0_and_1 -from [get_registers $source_registers] -to [get_registers $destination_registers]

Do not apply a set_false_path constraint on the path, as this constraint overrides set_data_delay constraints.

Severity

High

Tags

Tag Description
cdc-bus  

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10
  • Intel® Stratix® 10
  • Intel® Agilex™