altsource_probe Intel FPGA IP

Parent topic: altsource_probe Intel FPGA IP

Output Ports

Port Name	Required	Description	Comments
source[]	Yes	Specifies the `source` port.	Output port `[source_width - 1..0]` wide.

Parent topic: altsource_probe Intel FPGA IP

Contact Intel | Terms of Use | Trademarks | Privacy | Send Feedback

Copyright© Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.