TMC-20017: Loops Detected

Description

Violations of this rule show that strongly connected components (logical loops) exist in the design netlist. These loops prevent proper timing analysis. Run check_timing to show all components of the loops.

Recommendation

Remove the loops in your design.

Severity

High

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10
  • Intel® Stratix® 10
  • Intel® Agilex™