RES-30134: Registers Not Reachable from Reset Release IP

Description

Violations of this rule identify registers that are in feedback paths and are also unreachable from the Reset Release Intel FPGA IP. These registers may exit reset before device configuration completes.

Recommendation

Connect the Reset Release Intel FPGA IP such that the signal can propagate to registers in feedback loops. Refer to Including the Reset Release Intel FPGA IP in Your Design in the Intel Stratix 10 Configuration User Guide for more details.

Severity

Medium

Device Family